Note: This project is currently shelved after the first spin-up revision. Power-on testing was completed but the layout requires further work before the design is flight-ready.

UoBSAT SoM Interface Board

University of Bristol Satellite Programme KiCad 8 | CubeSat | Space Application

What this is

This is the compute and payload interface board for the University of Bristol satellite. It hosts a Variscite DART-MX8M-PLUS system-on-module and handles power conditioning, protection, and the connections needed to run a pair of Xenics MicroCube 640 LWIR thermal cameras over Ethernet.

The previous design used a BeagleBone Black with a custom hat stacked on top — physically large, unreliable board-to-board connections, and not much compute headroom. This replaces that with a single carrier board in the Nanopower P31U dock form factor, which is what the satellite structure and PDU are already built around.

System overview

Nanopower PDU (P31U / P60 Dock)
         │
         │  Dual redundant power feeds
         ▼
┌─────────────────────────────┐
│   SoM Interface Board       │
│                             │
│  Power OR ──► TPS2660 eFuse │──► DART-MX8M-PLUS SoM
│  (redundant)  TPS62918 Buck │         │
│                             │         │ Gigabit Ethernet
│  ADS1119 ADC (telemetry)    │         ▼
│  TMP102 temperature sensor  │  Xenics MicroCube 640
│                             │
└─────────────────────────────┘

The P31U is the standard PDU for small satellites — it distributes bus power to payload modules in a PC/104-style stack. This board sits in one of those slots.

Compute module — Variscite DART-MX8M-PLUS

The main reason for moving away from the BeagleBone was the combination of size and compute. The BeagleBone + hat arrangement took up two stacked PCBs and was running a single-core Cortex-A8 at 1 GHz with no ML capability at all.

The DART-MX8M-PLUS SoM is built around the NXP i.MX 8M Plus — quad-core Cortex-A53 at 1.8 GHz, a Cortex-M7 for real-time tasks, and a 2.3 TOPS NPU on-chip. The NPU is the main reason I went with this SoC; thermal image processing (hot-spot detection, anomaly flagging) can run locally without needing a ground link, which matters a lot when you only have contact windows of a few minutes per orbit.

The M7 core handles hard-deadline camera control and telemetry without competing with the main OS scheduler. That separation is something you can’t easily do on a single-core system.

The SoM integrates DDR4, eMMC, and power management, so the carrier only needs to deal with the interfaces the mission actually uses. Much simpler than designing around a discrete SoC.

The SoM connects to the carrier via three Hirose DF40C-90DS-0.4V mezzanine connectors. These are 0.4 mm pitch surface-mount connectors rated for launch vibration — the BeagleBone used pin headers which are explicitly not rated for that.

Power architecture

The PDU provides two independent power feeds per module for redundancy. The board needs to combine them without introducing a single point of failure in the combining circuit itself.

Redundant power OR

I initially looked at using Schottky diodes to OR the two inputs — it’s the obvious approach. The problem is the forward voltage drop: at 5 V bus you’re losing 300-400 mV per diode, which is 6-8% efficiency gone as heat with no recovery path. In a vacuum that heat has nowhere to go except into the board.

Instead I used a comparator-based OR circuit with MOSFETs as the pass elements. R_DS(on) is one to two orders of magnitude lower than a Schottky junction, so the drop is negligible. I looked at using the LTC4412 which implements this in a single package, but ended up going discrete so I could tune the thresholds to the exact voltages the Nanopower PDU provides.

TPS2660 eFuse

Every power rail passes through a TPS2660 eFuse before reaching the load. The main things I needed were: 4 V minimum operating voltage (so it stays alive as the bus droops under peak load), overcurrent and overvoltage protection, and some consideration for the space radiation environment.

The TPS2660 has adjustable current limiting via a single resistor, slew rate control on the output to manage inrush, and integrated reverse polarity protection (useful during ground integration when things get connected backwards). The SEL protection was actually the deciding factor over the LTC4364 — if a heavy ion triggers a latch-up in a downstream CMOS device, the resulting current surge trips the eFuse before thermal damage occurs. It’s not a substitute for radiation-hardened parts, but it’s meaningful protection for a low-cost mission.

TPS62918 synchronous buck converter

The SoM needs 3.3 V and the cameras need 5 V. The PDU bus voltage varies with battery and solar state, so a buck converter is needed. I used the TPS62918 — 3 MHz, 3 A, synchronous topology. The synchronous rectifier (MOSFET low-side instead of a diode) recovers the rectifier loss that a non-synchronous converter would waste. At 3 MHz the switching noise sits well above the ADC and analogue signal frequencies, which simplifies filtering. Fixed-frequency operation keeps the spectral content predictable.

Power monitoring — ADS1119

The ADS1119 is a 16-bit delta-sigma ADC over I2C. It monitors voltages and currents across the power rails so the SoM can downlink housekeeping telemetry. Sixteen bits gives about 78 µV resolution on a 5 V rail, which is enough to see meaningful sag without being buried in noise. The differential input mode means I can measure across a shunt resistor directly without a separate instrumentation amplifier.

If an eFuse is tripping repeatedly, the ground team should be able to see it in the housekeeping data.

Temperature monitoring — TMP102

A TMP102 digital temperature sensor sits near the power components. In a vacuum there’s no convective cooling path, so a temperature reading out of range is an early warning of a thermal problem. The TMP102 has a programmable alert threshold that connects to a GPIO on the SoM, so firmware can respond to a thermal event without waiting for a ground command.

Camera interface — Xenics MicroCube 640

The MicroCube 640 is a LWIR thermal camera (8-14 µm, uncooled VOx microbolometer, 640×512 pixels) that outputs calibrated imagery over Gigabit Ethernet. The GigE interface was a large part of why I selected it — the i.MX 8M Plus has an integrated GigE MAC, so no external USB host controller or PCIe bridge is needed. The camera just appears as a network device to Linux, which means standard image acquisition tools work with it out of the box.

Frame size for 640×512 at 14-bit depth is around 655 kB. At 25 fps that’s about 130 Mbps sustained — well within what GigE can handle.

The 5 V camera rail has its own dedicated TPS2660 instance. The camera is the highest-power peripheral and the most likely to exhibit inrush behaviour; isolating it means a camera fault can’t drag down the SoM supply.

Form factor

The board outline matches the Nanopower P31U dock reference. This means it slides into the satellite chassis without any mechanical rework, mounting holes line up with the existing standoffs, and thermal paths to the chassis can be planned from the start.

Component selection for the space environment

None of these components carry a formal MIL-SPEC or ESA space qualification — that’s out of scope and budget for a university CubeSat. The approach is to select industrial-grade parts with wide temperature ranges, avoid component families known to have problems in space, and document the reasoning so the design can be reviewed or upgraded later.

Temperature

LEO at 400 km cycles a board roughly between -20°C and +60°C under nominal conditions, with wider extremes during eclipse transitions. The design margin target is -40°C to +85°C — standard industrial grade. Most of the ICs have +125°C upper limits, so there’s 40°C headroom on the hot end.

The two constraints that are tighter than everything else:

• DART-MX8M-PLUS is rated to +85°C junction — exactly at the target, no headroom. In a vacuum the junction temperature is purely driven by the thermal resistance from die to chassis, so the layout has to provide a good conduction path.
• MicroCube 640 is rated to +70°C operating — 15°C below the industrial grade standard and the tightest constraint on the board. This drives the thermal budget for the whole assembly. The camera’s isolated 5 V supply can be shut down if a thermal exceedance is detected, giving firmware a way to respond without ground intervention.

Capacitor dielectrics

No aluminium electrolytic capacitors — the electrolyte outgasses in vacuum and the capacitance drifts. Tantalum electrolytics are avoided where possible; they can fail short-circuit under surge conditions, which is more dangerous on a power rail than an open-circuit failure.

All decoupling and filtering capacitors are MLCC. X7R ceramic (±15% over -55°C to +125°C) for bulk decoupling. C0G/NP0 (±30 ppm/°C) for the precision filter and timing capacitors on the ADS1119 analogue inputs, where a temperature-dependent capacitance shift would move the filter corner and introduce a measurement error.

Y5V and Z5U dielectrics are not used — they can lose up to 80% of rated capacitance at cold temperatures.

Inductors

Ferrite core inductors rather than powdered iron. Powdered iron has better saturation current handling but the permeability varies more with temperature, which shifts the buck converter’s compensation and can cause instability at temperature extremes.

Radiation

None of the parts are radiation-hardened. For a one-year mission in LEO at 400 km, total ionising dose is roughly 5-10 krad(Si), which is within the tolerance of most modern commercial CMOS processes. Single-event latch-up is the bigger concern — the TPS2660 provides system-level SEL mitigation by detecting the resulting overcurrent and cutting the supply before thermal damage occurs. It’s not a complete solution but it’s meaningful protection for the mission profile.

PCB layout

Thermal management in vacuum

Without convective cooling, every component’s junction temperature depends entirely on how well heat conducts to the chassis. A few things that follow from this:

Power-carrying traces are derated 50% from IPC-2221 free-air values — those tables assume still-air cooling which doesn’t exist in orbit.

The TPS62918 and TPS2660 packages have exposed thermal pads on the underside. These sit above an array of filled thermal vias (0.3 mm drill, plugged to prevent solder wicking) connecting to the ground plane and down to the chassis contact area at the board edge.

The SoM footprint has a large copper area underneath connected by thermal vias to the bottom pour. The MAC8 standoffs mount the SoM to the carrier and provide the primary thermal contact path to the board.

Vibration

All components are surface mount — through-hole component leads act as lever arms under vibration and the solder fillet at the PCB surface is the fulcrum. The Hirose DF40C connectors are rated for 2G vibration; the mated height of 0.4 mm and the 90-pin clamping distributes the mechanical load across the whole interface.

The SoM standoffs are at the corners of the SoM footprint so the SoM’s inertial load goes into the carrier at four points, not just from the connector locations.

Gigabit Ethernet traces

Differential pairs routed at 100 Ω ±10% differential impedance. Lengths matched within a pair to 0.1 mm with serpentine sections. Inter-pair matching to within 5 mm. Reference planes are uninterrupted under the GigE routing channel — any split in the return plane forces the return current to detour around it and turns the trace into an antenna. The pairs stay on a single layer from the SoM connector to the camera connector to avoid via stubs on the high-speed signal.

ADC layout

The ADS1119 sits in a quiet corner of the board. The ADC’s AGND and DGND connect to the same plane at the IC, but the ground copper is arranged to steer high-frequency digital return currents away from the analogue sensing area. Each analogue input has a 100 Ω / 10 nF RC filter at the PCB entry point — anti-aliasing and ESD current limiting. The corner frequency is around 160 kHz, which is well above the 1 kSPS ADC rate but well below the 3 MHz switcher. A guard ring surrounds the analogue section.

Test points

Test points on every power rail, I2C bus, and key GPIO signals, on the bottom copper layer outside the SoM footprint. The board gets assembled and tested before it goes into the satellite stack, at which point most connectors are inaccessible — test points allow verification at that stage.

Via tenting and via-in-pad

Vias are left open (no solder mask tenting). In space, flux or contamination trapped under a tent can outgas slowly in the low-pressure environment. Open vias can be fully cleaned during the wash process.

Via-in-pad under the TPS2660 and TPS62918 thermal pads uses filled and plated-over vias — otherwise solder wicks down the barrel during reflow and leaves voids in the thermal pad joint.

Conformal coating

After assembly and test the board gets a parylene conformal coat (12-25 µm, chemical vapour deposition). Parylene deposits as a pinhole-free film that follows all surface topography including under components — it outperforms liquid-applied coatings in this respect. The test points are masked before coating.

Skills demonstrated

• KiCad 8 — hierarchical schematic capture, custom footprint creation, 3D model integration, PCB layout with impedance control and thermal management
• Power electronics — synchronous buck converter design, eFuse selection and threshold calculation, redundant power-OR topology, derating for vacuum
• Space systems — radiation effects (SEL, TID), thermal management without convection, telemetry architecture, launch vibration and shock
• Signal integrity — Gigabit Ethernet differential pair routing, impedance control, return path continuity, length matching
• Analogue layout — ADC input filtering, guard rings, decoupling hierarchy, ground plane partitioning
• Component selection — temperature grade trade-offs, capacitor dielectric selection, inductor core material, ESD and SEL protection
• Platform selection — SoM vs SBC trade study, driver ecosystem considerations, real-time co-processor architecture